30 Aug 2022 (Tue) - 07 Sep 2022 (Wed)
01:00 PM - 02:00 PM
The Webinar will provide an overview of the AMD Xilinx ZYNQ Ultrascale plus architecture and family.
This is followed by an introduction to designing using the Vivado IP integrator.
We will then create and customize a MPSoC system using Vivado and IP Integrator , build and implement the FPGA design, and perform the hardware handoff for further software.
In this Webinar, we will, over the course of approximately one hour, provide an introduction to Vitis SDK. Then using the hardware designed in Webinar session I, we will build and run a bare-metal application with Vitis SDK on the MPSoC’s Application Processor Unit and the R5 processor unit.
This will then set us up nicely for the third Webinar.
In this Webinar, we will, over the course of approximately one hour, provide an introduction to Petalinux.
Following this, we build an embedded Linux system based on the hardware designed in Webinar I (used in the previous two webinars).
Then we will boot Linux on the hardware designed.
AMD Xilinx Product Manager at Excelpoint ANZ. He has over 20 years’ experience in the electronics industry with a long association with AMD Xilinx.
AMD Xilinx FAE Manager at Excelpoint ANZ. He has over 20 years’ experience as an FPGA design engineer, working in wired/wireless and space technologies.